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Piezo-Electric Actuator Controller
Preliminary Technical Data
FEATURES
Two Efficient Class D-type Amplifiers Six Integrated Pattern Drivers Programmable Output Drive Patterns 12-bit ADC Voltage or Current Sensing for Position Feedback Programmable Shutter Control On board temperature sensing Optional Off-board Temperature Sensing 32-lead 5mm X 5mm LFCSP Package
AD5801
FUNCTIONAL BLOCK DIAGRAM
LDO1
APPLICATIONS
Camera Phones Piezoelectric Positioning Piezo Actuators Lens Auto focus Lens Zoom Iris/Exposure NDF Neutral density Filter Shutter Camera Phone Camera Enabled PDA Camera/Image Modules Digital Still Camera DSC Web Cameras Security Cameras Digital Camcorders
LDO2
Figure 1. AD5801 Functional Block Diagram.
PRODUCT HIGHLIGHTS
1. Eight independent output drivers. 2. Available in 32-Lead (5mm X 5mm) LFCSP package.
GENERAL DESCRIPTION
The AD5801 is a high efficiency ultrasonic motor controller with two Class D-type output drivers. These Class D-type drivers can be used independently or configured as an H-bridge driver, and have full pattern programmability. There are also six integrated drivers which can be operated independently and have programmable output patterns. The AD5801 also has integrated drivers which are programmable from 130mA to 200mA, and may be used for a combination of Shutter and NDF/IRIS control. The operation modes of the drivers are invoked by the AD5801 using an I2C compatible interface. The I2C address for the AD5801 is TBD.
3. Multiplexed input 12-bit resolution ADC for voltage or current measuring. 4. Dual temperature sensing feature, Integrated AD5801 temperature sensing and optional external temperature reading of position sensor. 6. Low Ron in Auto Focus driver switches, 0.5 max. 7. Fully guaranteed in the 2.8 V to 4.5 V supply range. 8. Integrated Shutter/Iris/NDF optional controls
ev. 0 | Page 1 of 13
AD5801 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings....... Error! Bookmark not defined. ESD Caution.................................................................................. 5
Preliminary Technical Data
I2C Timing Characteristics..............................................................6
REVISION HISTORY
June/05--Revision 0.9
Rev. 0 | Page 2 of 13
Preliminary Technical Data SPECIFICATIONS1
VCC = 2.8V to4.5 V, VCC>VDD, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter Driver Stage2 Switch On Resistance PMOS (high switch) NMOS (low switch) Driver Stage2 Drive Current Capability Output High Voltage Output Low Voltage Analog to Digial Converter Position Sensing Resolution INL DNL Conversion Time3 Input Voltage Range in Current Sense Mode Current Range Input Voltage Range in Voltage Sense Mode Integrated Temperature Sensor Resolution Range Accuracy Conversion Time External Temperature Sensor Resolution Range Input Voltage Range Conversion Time3 Input Voltage Range Input Voltage at POSSENS1 Symbol FA, FB Ron Conditions Min Typ1
AD5801
Max
Unit
0.5 0.5 FC, FD, ZA,-ZD VOH VOL ADC 12-bit LSB 12-bit LSB Max Voltage at SENSE Source Current from SENSE 8 2.4 0.8 12 1 1 160 0 0 2 -30 +/-4 320 70 1.5 300 TBD
mA V V LSB LSB LSB s V A V C C C s C C V s V
-30 160
70
1.5
Rev. 0 | Page 3 of 13
AD5801
BIAS Bias reference Voltage Output Current range Output Current Accuracy External Resistor4 External Resistor Tolerance Shutter Controls Output Current Range Accuracy5 Step Size Shutter Strobe Strobe Time Input High Voltage Input Low Voltage Low Drop Out Regulator6 Programmable Output Voltage Range Output Current Drive Capability Accuracy5 Programmable Output Voltage Level 1 Programmable Output Voltage Level 2 Programmable Output Voltage Level 3 Programmable Output Voltage Level 4 LDO Compensation Capacitor External Clock7 Clock Frequency Range Internal Clock7 Clock Frequency I2C Interface8 SDA, SCL Input High Voltage SDA, SCL Input Low Voltage Glitch Rejection ShutDown/Standby/RESET9 XSD High Level Input voltage XSD Low Level Input voltage Minimum Valid Shutdown period Min Time Between Successive XSD Pulses Power Supply VBATT Currrent Consumption in Active Mode Current on VBATT VAUX Current on VAUX PWR_DRIVESTAGE SHUTTER_VBATT PWR_DRIVERS BIASRES Current to POSSENSAF-Z Rterm
Preliminary Technical Data
1.275 10 2.5 5.1 V mA % k % mA % mA ms V V V mA % V V V V F MHz MHz V V ns V V ns ns V mA mA V A V V V
4
19
-1 SOUT1-SOUT3 130 10 STROBE VIH VIL LDO_ACT 5 1.17
1 200 5
35 0.63
2.8
3.3 200 3 2.8 2.9 3.0 3.3
10 EXTCLK 4.8 INTCLK
20 19.44 19.44
VIH VIL XSHUTDOWN
1.3 0
1.8
VAUX 0.4 50
1.17 0.63 100 TBD Battery Supply 2.8 4.5 TBD TBD VBATT TBD 5 5 5
Digital Supply FA-FB Drivers Shutter Supply FC, FD, ZA-ZD Drivers
2.5 2.5 2.5 2.5
1 1
Temperature range is as follows: B Version: -40C to +70C See Figure 3 for timing programmability details. 3 The conversion time of 160s is due to averaging of four measurements taken by the ADC,. The averaging feature can be disabled and the conversion time is then 40s. 4 An external precision resistor is required to establish bias currents and voltages. 5 This is the accuracy over the entire temperature range. Rev. 0 | Page 4 of 13
Preliminary Technical Data
6 7
AD5801
A minimum 10F capacitor is required for LDO_ACT. A 4.7 F is required at the pin LDO2_COMP. The AD5801 can be programmed for use with an external or internal clock. 8 See Table 3 and Figure 2 for I2C timing specifications. 9 Bringing XSHUTDOWN low disables the I2C interface, on a low to high transition there is a reset on the AD5801.
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters VCC to GND Digital Inputs Voltage on Analog Inputs DRPWR pins to GND FOUT pins to GND ZOUT pins to GND Maximum Voltage between GND pins1 Operating Temperature Range Storage Temperature Range Junction Temperature 32-Lead LFCSP JA Thermal Impedance Lead Temperature, Soldering (10 s)
1
Rating TBD -0.3 V to (VDD + 0.3 V) -0.3 V to (VCC + 0.3 V) -0.3V to TBD -0.3V to TBD -0.3V to TBD 0.3V -30C to +70C -65C to +150C 150C 32C/W 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
This is the maximum allowable voltage between the various GND pins on the AD5801.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 13
AD5801
Preliminary Technical Data
Table 3. I2C Serial Interface
Parameter1 FSCL t1 t2 t3 t4 t5 t62 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.1 CB 400 Unit kHz max s min s min s min s min ns min s max s min s min s min s min ns max ns min ns max ns min ns max ns min pF max Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT data hold time tHD, DAT data hold time tSU, STA setup time for repeated start tSU, STO stop condition setup time tBUF, bus free time between a stop and a start condition tF, fall time of SDA when transmitting tR, rise time of SCL and SDA when receiving (CMOS compatible) tF, fall time of SDA when transmitting tF, fall time of SDA when receiving (CMOS compatible) tF, fall time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line
CB3
1 2
See 2. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of SCL's falling edge. 3 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START CONDITION
t6
t2
t5
t7
REPEATED START CONDITION
t1
t8
STOP CONDITION
03773-0-007
Figure2.. I2C Interface Timing Diagram
Block Diagram
Rev. 0 | Page 6 of 13
Preliminary Technical Data
Table 3. Pin Function Descriptions
Pin. No. Mnemonic SHUTTER_VBATT STROBE
AD5801
LDO2_COMP POSSENSE1 POSSENSE2 POSENSAF POSENSZ BIASTRES XSHUTDOWND SCL SDA EXTCLK DIG_GND VAUX ZD ZC ZB ZA FD FC PWR_DRIVERS GND_DRIVESTAGE FB FA PWR_DRIVESTAGE LDO_ACT VBATT ANAGND SHUTTER_GND
SOUT1 SOUT2 SOUT3
Description Power Connection for the Shutter Drivers SOUT1-SOUT3, to be connected to VBATT Duration of the STROBE signal width sets the duration of current pulsed from SOUT1 to SOUT3. The STROBE function can be disabled and the pulse duration can be programmed over the I"C interface if required. This is the compensation pin for the internal Low Drop Out Regulator LDO2. A 4.7F capacitor should be connected between LDO2_COMP and ANAGND. Input to ADC, the AD5801 can be used to measure current in an opto-reflective position feedback scheme,or voltage from a Hall sensor or some other voltage output sensor, to determine lens postion. Input to ADC, the AD5801 can be used to measure current in an opto-reflective position feedback scheme,or voltage from a Hall sensor or some other voltage output sensor, to determine lens postion. Programmable current output. Programmable current output. Connected to external resistor for bias current generator Asynchonous system reset signal I2C Interface Signal I2C Interface Signal Optional External Reference Clock Signal Digital Ground Digital Supply Pattern programmable output driver which can be used for zoom control. Pattern programmable output driver which can be used for zoom control. Pattern programmable output driver which can be used for zoom control. Pattern programmable output driver which can be used for zoom control. Pattern programmable output driver which can be used for auto focus control. Pattern programmable output driver which can be used for auto focus control. Power Supply pin for pattern programmable putput drivers FC, FD, ZA, ZB, ZC, and ZD. This pin can be connected to LDO_ACT or a supply of 5V max. Ground for Focus Actuator/Motor Drivers FA and FB and for pattern drivers FC, FD, ZA, ZB, ZC, and ZD. Pattern programmable low Ronoutput driver which can be used for driving auto focus piezo actuator directly. Pattern programmable low Ronoutput driver which can be used for driving auto focus piezo actuator directly. Supply for low Ron Drivers FA and FB, can be connected to LDO_ACT or a supply of 5V max. Output of integrated Low Drop Out Regulator. A 10F decoupling capacitor should be connected between LDO_ACT and ANAGND. Battery supply connection. Analog Ground connection. Ground connection for Shutter Drivers SOUT1-SOUT3, this pins should be connected to ANAGND and special care should be exercised to ensure that the ground return path from this pin to ANAGND is kept to a minimum impedance. Output for Shutter/Iris/NDF/Lens Cover Drive and control. Output for Shutter/Iris/NDF/Lens Cover Drive and control. Output for Shutter/Iris/NDF/Lens Cover Drive and control.
Rev. 0 | Page 7 of 13
AD5801
General Description The AD5801 is a high efficiency ultrasonic motor controller with two Class D-type output drivers. These Class D-type drivers can be used independently or configured as an H-bridge driver, and have full pattern programmability. There are also six integrated drivers which can be operated independently and have programmable output patterns. The AD5801 also has integrated drivers which are programmable from 60mA to 200mA, and may be used for a combination of Shutter and NDF/IRIS control. The operation modes of the drivers are invoked by the AD5801 using an I2C compatible interface. Driver Stage for Auto Focus Channel FA sad FB are Class D-type outputs with an onresistance, Ron, of 0.5 maximum over temperature. These outputs have been integrated to eliminate the need to use external FET drivers for the Auto Focus function and can be configured as a PWM source. The driving frequency of outputs FA and FB is configured in the Registers PWUNIT and PWMPERIOD. The PWUNIT defines the basic time interval from when the counters can
Preliminary Technical Data
derive a count, and is used to set the divide factor used to divide the clock frequency of the master clock derived from the integrated PLL in the AD5801, or the clock applied to EXTCLK. The effective phase difference in the outputs FA and FB can be programmed in the PWMAFATx and PWMAFBTx registers, and the waveforms can be programmed with varying or constant duty cycles (See Figure 3). The PWM patterns from Channels FA and FA are enabled in the PWMENABLE and PWMPOLARITY Registers. The PWMENABLE register allows the user to enable the drivers channels required, the PWMPOLARITY Register is used to set the polarity of the drive patterns when they are initiated. When the outputs are disabled they can be set configured in a High Impedance, or High or Low state. To move the motor in reverse the user has the choice of either setting new values to the PWMAFATx and PWMAFBTx registers or setting a direction bit in the ACTIVE Register which interchanges the timing values between the driver outputs FA and FB. The actual duration of the drive operation is defined in the AFSTEPS Register, this allows the user to enter the number of PWMPERIODS required for one move of the lens.
PWMPERIOD
PWM FA
PWMAFAT1
PWMAFAT2
PWM FB
PWMAFBT1
PWMAFBT2
Figure 3. Timing Diagram for Class D-type Driver FA and FB.
Driver Stages FC - ZD Drivers FC, FD, and ZA - ZD are independent driver channels capable of driving 8mA. These channels can be configured as PWM drivers and used to drive external FETs or Bridges for Zoom control, or for other timing functions.
As with Drivers FA and FB the driving frequency is programmed in the PWMUNIT and PWMPERIOD Registers, and the programmed PWM patterns are enabled by the PWMENABLE and PWMPOLARITY Registers. These driver outputs have four registers (PWMAFCTx, PWMAFDTx, PWMAZATx - PWMAZDTx ) which allow the user to
Rev. 0 | Page 8 of 13
Preliminary Technical Data
programme up to four transitions within the time set in the PWMPERIOD Register (See Figure 4 for typical timing diagrams, with outputs FC and FD as an example).
AD5801
The number of PWMPERIOD periods is again set in the AFSTEPS and ZSTEPS Registers. When the outputs are disabled they can be set configured in a High Impedance, or High or Low state.
PWMPERIOD
PWM FC
PWMAFCT1 PWMAFCT2 PWMAFCT3 PWMAFCT4
PWM FD
PWMAFDT1 PWMAFDT2 PWMAFDT3 PWMAFDT4
Figure 4. Timing Diagram for PWM Drivers.
programmed in these Registers. Temperature Compensation of Drive Patterns Because of the high temperature coefficients associated with piezo elements fine tuning of the drive pattern and drive frequencies are required to ensure the device operates over its intended temperature range. In all drive modes it is possible to specify different timing parameters for three different temperature areas.. If Temperature compensation mode is selected by programming the appropriate bit to the DRIVEMODE register, the PTAT temperature is checked at the beginning of the new ACTIVE move command and depending on the Temperature recorded the timing data for the move is read from the appropriate timing register, HOT, COLD or NOMINAL. The timing registers for all the driver outputs FA-ZD are duplicated for Hot and Cold operation and the relevant timing information for the Hot and Cold bands of operation are PWM Slope Mode A piezo element is a block of ceramic material and is basically a moving capacitor. The electrical energy of the drive patterns are converted into mechanical reaction energy inside the piezo element, and the resulting deformation in the material is used to produce forces to move the lens assembly in an optical module. Driving a capacitive element with digital patterns may produce large surges in power because power is only consumed during transients and the impedance of the piezo motor can be very small on the rising and falling edges of a pulse. TheAD5801 has an alternative driving scheme called the PWM Slope Mode which can be employed on Channels FA and FB. The Slope Mode allows the user to control the rise and fall times of the drive waveform by taking advantage of the energy storage properties of the series inductor and the resultant LC
Rev. 0 | Page 9 of 13
AD5801
filtering when combined with the piezo element. The AD5801 Slope Mode effectively allows the user to control the rise and fall times of the drive waveform by using predetermined PWM patterns and driving these patterns into an LC load. The AD5801 have several default patterns, which after filtering by the addition of a suitable inductor in series with the capacitance of the piezo load, produces a rhombic or triangular waveform at the piezo element. The principle on which this mode works is that the pattern density increases linearly and then decreases linearly from:
1 X
G
Preliminary Technical Data
AD5800 Slope Mode Pattern
G
Resultant Waveform across Piezo Element due to Filtering
X X
Figure 5. AD5801 Slope Mode Pattern and resulting filtered waveform across the piezo motor.
Where: X is 8, 9, 10 or 11 The default patterns are register selected and allow the user to effectively control the rise and fall times of the waveforms across the piezo motor. The AD5801 PWM Slope Mode pattern causes the waveform across the piezo element to ramp from GND to an output high level defined by the supply voltage connected to the PWR_DRIVESTAGE pin. The period set in the PWMPERIOD register defines the high and low time within one period. For example: if selected X value = 10 and PWMPERIOD = 254 Then the number of counter periods, as defined in the PWNUNIT register that are on the top and bottom of the resultant waveform are calculated with the following Formula: Number of Periods = The primary advantage of using the AD5801 in Slope Mode is that the rise and fall times of the driving waveform are controlled, and therefore the power surges associated when driving the piezo element with a square wave at its resonant frequency are eliminated. Clock Generation The AD5801 offers the user the choice of two master clock sources, an internal clock generated from an integrated VCO, or an external clock applied through the EXCLK pin. The external reference clock is provided by the baseband processor in the host system, and can be either a DC coupled square wave or an AC coupled sine wave. In either case the clock may have been RC filtered. The clock may be either a free running system clock or dedicated camera module clock, which may be enabled and disabled by the host. The AD5801 has a highly accurate PLL based clock generator which accepts an accurate and stable multiple of the external clock (4.8MHz or 9.6MHz), and multiplies its frequency to the master clock of 19.44MHz required by the AD5801. The AD5801 also has the option of using an integrated clock generator. The MCLKCONTROL Register allows the user to select either the external or integrated clock source, select. If an external clock is used then the MCLKCONTROL Register allows the user to set the AD5801 EXTCLK pin to accept an AC-coupled or DC-coupled clock, and also allows the user to select the master clock frequency supplied, or to bypass the PLL if the master clock is 19.44MHz. The internal clock is generated using a 2% accurate VCO. ADC and Lens Position Sensing The AD5801 has an integrated on board 12 bit ADC. The ADC contains an on-chip track and hold amplifier, a successive approximation A/D converter. Clocking for the A/D is provided using a divided down ratio of the integrated or host master reference clock.
PWMPERIOD - X 2 x 2 2
[
]
In the case where X = 10
Number of Periods =
254 - 10 x 2 = 26 2
2
[
]
So there are 26 counter periods on top and bottom of the resultant rhombic waveform. Figure 5 illustrates the AD5800 driving a default PWM Slope Mode pattern through a series inductor and into the piezo load, and the resultant waveforms.
Rev. 0 | Page 10 of 13
Preliminary Technical Data
A programmable safety interval is allowed to elapse before the actual position measurement is made by the ADC. This safety interval duration can be set in a register to be anything from zero to 1000s. Four consecutive measurements from the lens position signal are made and their average saved to result registers. Each of the lens position measurement results are stored in two 8-bit registers because the ADC is a twelve-bit converter. It is possible to turn-off the averaging feature if required. The ADC has the ability to accept either current or voltage inputs depending on the position sensing scheme used. A bit in the CONFIG register will set the AD5801 for current or voltage conversion. Figure 6 show a simplified diagram where the ADC measures the output of an optical reflective position sensor. Depending on whether it is the auto focus lens position or Zoom position you are measuring the IDAC sources a current derived from an integrated Bias circuit and external precision resistor, BIASRES. The Bias circuit consists of bandgap voltage reference and current to voltage generator. The current sourced is between 4mA and 19mA with 4-bit resolution. In the case of an auto focus lens position measurement the desired current is programmed to LED, D1. The incident light from D1 falls on the photosensitive device Q1 . The output of Q1 is connected to the POSSENSE1 pin and the current flowing in Q1 is then measured by the ADC, and there is a direct current to lens position relationship which indicates the position of the auto focus lens. Because the zoom lens position LED, D2, has no current flowing in it then there is no current flowing in the photosensitive device Q2, and only the position of the auto focus lens is detected and measured. The position sensing for the zoom lens works on exactly the same principles.
AD5801
AD5801
OPTICAL REFLECTIVE POSITION FEEDBACK SCHEME
Figure 6. Lens position Sensing using an Optical Reflective Feedback Scheme. Figure 7 shows the ADC configured to measure in voltage mode. The inputs POSSENSE1 and POSSENSE2 can be connected to the outputs of HALL sensors, or POSSENE1 can be tied to AGND and POSSENSE2 can be used to measure single ended voltages, The AD5801 also has an internal register which may be programmed with a required threshold value, and this value can then be compared to the Hall voltage or single-ended voltage input. The threshold voltage can be used to indicate the ret position of either lens. For example, if the user is driving the lens to the start position the output of the comparator disables the output drivers when the programmed threshold indicating the lens start position is reached. Only one position sense measurement is performed at a time. For a zoom lens position measurement current is source from the POSSENSEZ pin into the Zoom Hall Plate, and the resulting voltage from the output of the Hall sensor is connected through the POSSENSE1 and POSSENSE2 pins to the ADC. Given that only one Hall Sensor is active at one time it is possible to connect the outputs of both sensors together. For single-ended sensor outputs the output voltage is connected to POSSENSE2 and POSSENSE1 is connected to AGND.
Rev. 0 | Page 11 of 13
AD5801
AD5801
Preliminary Technical Data
POSITION FEEDBACK SCHEME WITH HALL SENSOR
Figure 7. Lens Position Sensing using Hall Sensors.
Rev. 0 | Page 12 of 13
Preliminary Technical Data
AD5801
Outline Package Dimensions
Rev. 0 | Page 13 of 13

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